Tuesday, December 12, 2017

MEMSDrive OIS vs. VCM-based OIS

MEMSDrive publishes comparison videos of its OIS against iPhone X and Galaxy Note8 VCM-based OIS:

IEDM Papers Review

Semiconductor Engineering publishes Mark Lapedus review of IEDM 2017 Imaging Session papers:

- TSMC and EPFL presented "a paper on what they call the world’s first back-illuminated 3D-stacked, single-photon avalanche diode (SPAD) in 45nm CMOS technology.

The SPAD achieves a dark count rate of 55.4cps/μm2, a maximum photon detection probability of 31.8% at 600nm, over 5% in the 420-920nm wavelength range, and timing jitter of 107.7ps at 2.5V excess bias voltage at room temperature.

- Sony presented "a paper on a CMOS photon detector - a non-electron-multiplying CMOS image sensor photon detector. Based on a 90nm process, Sony’s CMOS photon detector features 15μm pitch active sensor pixels with a complete charge transfer and readout noise of 0.5 e- RMS.

The pixel circuit is a conventional 4T pixel. The pixels are arrayed, resulting in a high conversion gain of 132uV/e-, according to the paper. The photodiode is expanded to a size of 14.7μm x 13.1μm in a pixel with a pitch of 15μm, resulting in a physical fill factor of 76% without using back illumination. 4 pixels in a column are simultaneously accessed and read.

Samsung Improves its Iris Scanner

Korea Herald: The oncoming "Galaxy S9’s iris scanner will have an improved camera lens and functions to make it better to recognize the eyes of users.

The iris camera lens will be improved to 3MP from 2MP of Galaxy S8 and Galaxy Note 8 to capture clearer images. The scanner will better recognize users’ irises even when they wear eyeglasses, move their eyeballs or are in a too dark or too light environment. The response time will also be shorter from the current one second.

Samsung is also on target to expand the iris scanner into budget models possibly late next year or early 2019 with the ultimate aim of replacing physical banks with mobile banking.

A Samsung spokesperson said, “Iris scanner is the safest biometric authentication (among iris, fingerprint and face recognition) and we will continue to improve the system for upcoming smartphones for safer banking transactions.

Galaxy S8 iris scanning

MIPI Alliance Opens Access to its MIPI I3C Sensor Interface Specification

BusinessWire: Starting today, all companies, including those not currently members of MIPI Alliance, may access the MIPI I3C v1.0 specification so they may evaluate the incorporation of the specification into their sensor integration plans and design applications.

MIPI I3C provides a welcome update to the I2C technology that has been widely adopted over the past 35 years. Extending access provides an opportunity to spur innovation and help other industries beyond mobile," said Joel Huloux, chairman of MIPI Alliance. "It helps MIPI members as well, because it supports greater adoption and interoperability, strengthens the ecosystem and provides for a richer development environment.

Panasonic and Osaka University Develop Blood Vessel Endoscope

Asahi Shimbun: Panasonic and Osaka University have developed what they say is the world’s first vascular endoscopic catheter with an image sensor on its head that they say greatly improves blood vessel observations and could change existing therapies. The new catheter has a color resolution of about 480,000 pixels, about 50x higher than the existing devices.

An image sensor, a lens and a fiber-optic illuminator are embedded in the head of the vascular endoscopic catheter, which measures 1.8mm across and 5mm long.

Taisho Biomed Instruments Co., a manufacturer of medical devices, plans to release the new vascular endoscopic catheter for sale to hospitals this year. Panasonic has set a shipping target of about 8,000 units in fiscal 2021.

Synaptics Unveils 2nd Generation Under-display Optical Fingerprint Sensor

PC Perspective: Synaptics unveils FS9500 Clear ID family of optical fingerprint sensors for smartphones with OLED displays. Synaptics attaches a fingerprint senor module to the underside of the display and using the OLED display itself as the light source to illuminate the user's fingerprint so that the optimized CMOS image sensor can scan the fingerprint from the reflected light bounced through the gaps in between pixels. The new sensor can work with up to 1.5mm-thick displays.

Synaptics uses "Quantum Matcher" and "PurePrint" machine learning technology to enhance security and adapts to different external lighting environments, including a direct sunlight. The company says that its new fingerprint sensor is able to work faster and in more situations than a 3D facial recognition systems: its fingerprint sensor is able to read a user's fingerprint in 0.7s versus 1.4s for a facial recognition camera. The Clear ID In-Display fingerprint sensor is said to have approximately 99% spoof rejection rate due to the AI-powered PurePrint technology that discerns real fingerprints from fakes.

GlobeNewsWire: Synaptics is said to bring its in-display fingerprint sensors to mass production with one of the top five OEMs.

GlobeNewsWire: Synaptics's previous generation Natural ID FS9100 family of optical-based, under-glass fingerprint authentication solutions have been named a CES 2018 Innovation Awards Honoree. The Natural ID FS9100 family is said to be the industry’s first optical-based fingerprint sensors for smartphones enabling secure authentication through 1mm thick cover glass.

Synaptics is currently sampling its third-generation optical solution for in-display fingerprint authentication to select customers with mass production with a Tier 1 OEM expected in the current calendar year.

Monday, December 11, 2017

12nm Pixel Size

There is a funny mistake in Xiaomi Redmi 5 Plus smartphone promotional video:

2-step Column-Parallel Delta-Sigma ADC

CentraleSupelec, France, publishes a paper "A 14-b Two-step Inverter-based Σ∆ ADC for CMOS Image Sensor" by Pierre Bisiaux, Caroline Lelandais-Perrault, Anthony Kolar, Philippe Benabes, and Filipe Vinci dos Santos presented at IEEE International NEWCAS Conference, in June 2017 at Strasbourg, France.

"This paper presents a 14-bit Incremental Sigma Delta (IΣ∆) analog-to-digital converter (ADC) suitable for a column wise integration in a CMOS image sensor. A two-step conversion is performed to improve the conversion speed. As the same Σ∆ modulator is used for both steps, the overall complexity is reduced. Furthermore, the use of inverter-based amplifiers instead of operational transconductance amplifier (OTA) facilitates the integration within the column pitch and decreases power consumption. The proposed ADC is designed in 0.18 µm CMOS technology. The simulation shows that for a 1.8 V voltage supply, a 20 MHz clock frequency and an oversampling ratio (OSR) of 70, the power consumption is 460 µW, achieving an SNR of 83.7 dB."

Sunday, December 10, 2017

Imec Quantum Dot Sensor

MDPI Special Issue on the 2017 International Image Sensor Workshop (IISW) publishes Imec, KU Leuven, and Ghent University paper "Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors" by Pawel E. Malinowski, Epimitheas Georgitzikis, Jorick Maes, Ioanna Vamvaka, Fortunato Frazzica, Jan Van Olmen, Piet De Moor, Paul Heremans, Zeger Hens, and David Cheyns. The paper describes a somewhat similar to Invisage IR image sensor:

"This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors."

Saturday, December 09, 2017

Canon Global Shutter Sensor Paper

MDPI Special Issue on the 2017 International Image Sensor Workshop (IISW) publishes Canon paper "Development of Gentle Slope Light Guide Structure in a 3.4 μm Pixel Pitch Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology" by Hiroshi Sekine, Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Toshiki Tsuboi, Yasushi Matsuno, Hidekazu Takahashi, Shunsuke Inoue, and Takeshi Ichikawa.

"CISs with GS function have generally been inferior to the rolling shutter (RS) CIS in performance, because they have more components. This problem is remarkable in small pixel pitch. The newly developed 3.4 µm pitch GS CIS solves this problem by using multiple accumulation shutter technology and the gentle slope light guide structure. As a result, the developed GS pixel achieves 1.8 e− temporal noise and 16,200 e− full well capacity with charge domain memory in 120 fps operation. The sensitivity and parasitic light sensitivity are 28,000 e−/lx·s and −89 dB, respectively. Moreover, the incident light angle dependence of sensitivity and parasitic light sensitivity are improved by the gentle slope light guide structure."

Friday, December 08, 2017

Huawei is Reported Preparing Triple Rear Camera Smartphone

XDA Developers quotes Venturebeat reporter Evan Blass twitted about the oncoming Huawei smartphone featuring triple rear camera smartphone with 40MP resolution and 5x zoom:

Yole: Camera is Among Major Heat Sources in Smartphones

Yole Developpement report "Smartphones: a significant challenge for thermal management companies" points to camera and LED flash on one of the complex thermal management problems in smartphones:

Thursday, December 07, 2017

Recent ON Semi CCD Advances

MDPI Special Issue on the 2017 International Image Sensor Workshop (IISW) publishes ON Semi paper "Recent Enhancements to Interline and Electron Multiplying CCD Image Sensors" by Eric G. Stevens, , Jeffrey A. Clayhold, Hung Doan, Robert P. Fabinski, Jaroslav Hynecek, Stephen L. Kosman, and Christopher Parks.

"This paper describes recent process modifications made to enhance the performance of interline and electron-multiplying charge-coupled-device (EMCCD) image sensors. By use of MeV ion implantation, quantum efficiency in the NIR region of the spectrum was increased by 2×, and image smear was reduced by 6 dB. By reducing the depth of the shallow photodiode (PD) implants, the photodiode-to-vertical-charge-coupled-device (VCCD) transfer gate voltage required for no-lag operation was reduced by 3 V, and the electronic shutter voltage was reduced by 9 V. The thinner, surface pinning layer also resulted in a reduction of smear by 4 dB in the blue portion of the visible spectrum. For EMCCDs, gain aging was eliminated by providing an oxide-only dielectric under its multiplication phase, while retaining the oxide-nitride-oxide (ONO) gate dielectrics elsewhere in the device."

Queen Elizabeth Prize for Engineering Handed to Image Sensor Inventors

Queen Elizabeth Prize for Engineering has been presented to Eric Fossum, Nobukazu Teranishi and Michael Tompsett. Together with George Smith, who is unable to attend the ceremony, this year’s winners are honored for their contribution to creating digital imaging sensors:

From left to right: Prince Charles, Fossum, Tompsett, Teranishi

Qualcomm Snapdragon 845 Imaging Features

PRNewswire: The new Snapdragon 845 Platform is designed to capture cinema-grade videos and for AR applications:

Spectra 280 ISP:

  • Ultra HD premium capture
  • Qualcomm Spectra Module Program, featuring Active Depth Sensing
  • MCTF video capture
  • Multi-frame noise reduction
  • High performance capture up to 16MP @60FPS
  • Slow motion video capture (720p @480 fps)
  • ImMotion computational photography
  • Dual 14-bit ISPs
  • Hybrid Autofocus
  • Hardware Accelerated Face Detection
  • HDR Video Recording
Adreno 630 Visual Processing Subsystem:

  • 30% improved graphics/video rendering and power reduction compared to previous generation
  • Room-scale 6 DoF with SLAM
  • Adreno foveation, featuring tile rendering, eye tracking, multiView rendering, fine grain preemption
  • Improved 6DoF with hand-tracking and controller support

Hexagon 685 DSP:
  • 3rd Generation Hexagon Vector DSP (HVX) for AI and imaging

Wednesday, December 06, 2017

Leti SPAD Presentation

Leti publishes a presentation on SPAD image sensors it develops together with ST: "Avalanche Diodes for 3D Imaging at Large Distances" by Norbert Moussy. A few slides from the presentation:

Image Sensor Design Tutorials

CMOS Chip Designer site publishes a number of nice tutorials on image sensor design:

CMOS Image Sensors Overview - general Q&A
CMOS Pixel Design - starts from basics, does not go very far but still useful
Image Sensor Readout Circuits - ROIC - basic introduction, although some of the circuits do not represent the best practices, such as this one:

Column PGA and single-slope ADC with auto-zero

Update: The site owner took it offline. The content is still accessible for the next couple of days through Google cache by typing site:cmoschipdesigner.blogspot.com in the Google search field.

Update #2: The image sensor tutorials are back on-line.

Tuesday, December 05, 2017

Google on 3D Sensing in AR Applications

Google AR/VR head Clay Bavor comes up with a remarkable statement emphasizing imaging importance in AR applications:

Gigajot Licenses Binary Pixel Technology from Rambus

BusinessWire: Rambus announces that Dartmouth College-based startup Gigajot Technology has licensed Rambus Binary Pixel technology and patents for use in Gigajot’s next-generation image capture solutions. Gigajot’s Quanta Image Sensor (QIS) enables high-speed counting of single photons of light at gigapixel resolution. The new features enabled by QIS and Binary Pixel Technologies can benefit imaging applications such as scientific, automotive, security, defense, encryption, AR/VR, 3D and consumer photography, among others. Rambus has supported the early work at Dartmouth on the technology.

Rambus Binary Pixel technology combines an imager and a processor architectures to enable high quality images and video from small form factor imagers for compact solutions. The technology senses the photons using discrete thresholds to avoid pixel saturation and enable better light sensitivity. Binary Pixel also employs special oversampling methods, which subdivide pixels, exposure and digitization to capture more data and extend the dynamic range of the imager.

Traditionally, it has been difficult to achieve acceptable signal-to-noise ratio in low-light situations for quality images,” said Saleh Masoodian, CEO, Gigajot. “Combining the Rambus Binary Pixel technology with Gigajot’s QIS devices enables development of highly sensitive imaging technology via mainstream commercial CMOS fabrication processes for not only consumer devices such as smartphones, tablets and cameras, but also for more high-end commercial pursuits such as scientific, medical, security and surveillance sensors and cameras.

Rambus Binary Pixel technology enables improved performance for small, compact image sensors, allowing unprecedented image quality for consumer devices,” said Laura Stark, SVP and general manager, Emerging Solutions of Rambus. “Combining the Gigajot and Rambus cutting-edge imaging technologies will dramatically improve the image capture experience for the next generation of consumers and professionals.

As a matter of fact, Rambus Emerging Solutions web page does not list imaging technologies anymore. Neither the company product page lists any of the imaging technologies that Rambus developed in the past: HDR sensors, binary pixels, lensless imagers.

Yole Talk on TSV Technology

Most of the Yole Developpement webcast on TSV technology is devoted to stacked memory integration, but there is also some image sensor content, especially from 28:00 to 38:00 time:

TSMC 0.8um-0.9um Pixel Paper

MDPI Special Issue on the 2017 International Image Sensor Workshop (IISW) gets one more TSMC paper "A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel" by Seiji Takahashi, Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu, Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Wei-Chieh Chiang, Chun-Hao Chuang, Keng-Yu Chou, Chi-Hsien Chung, Kuo-Yu Chou, Chien-Hsien Tseng, Chuan-Joung Wang, and Dun-Nien Yaung.

"In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e− rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed."

A unit pixel circuit and device partition.
A 45 nm stacked CIS test vehicle.
TG area device optimizations
(a) Regular pixel; (b) crosstalk-improved pixel.

Espros Announces New Generation ToF Sensor

Espros announces epc611, a new generation 8×8 pixel ToF sensor. The epc611 is said to establish a new industry standard in terms of photon sensitivity, distance measurement frame rate and versatility for a wide range of applications. The small footprint of 2.6 x 2.6mm and bare die packaged epc611 will be produced in cooperation with TSMC.

Sensitivity: epc611 has a 30% enhanced sensitivity in comparison to previous generation ESPROS TOF sensors due to the latest generation TOF pixel design. Only 7.5 nW per millimeter-square of optical power is needed to measure accurately distance. And this under full sunlight condition.

Frame Rate: The epc611 allows up to 8’000 distance measurements per second.

Versatility: epc611 can be configured to operate in 7 different TOF modes. From an 8×8 imager to binning of all pixels into a single large pixel almost anything is possible. Groups of pixels can be configured to operate at different integration times or at different phase angles. In this way the imager can achieve a wide dynamic distance range or catch fast moving objects without generating motion blur.

«We put our entire experience in this new generation sensor», says Beat De Coi, CEO and founder of ESPROS Photonics. «I built sensors my whole life and know about the quite individual requirements that need to be satisfied. Therefore I wanted this chip to come with all configuration options that we could think of. And now its here!».

The new epc611 TOF sensor is available now. Several pilot customers have epc611 already in their labs. A first distance measurement module is under development and will be released soon.

Monday, December 04, 2017

IEDM Image Sensor Presentations

IEDM Image Sensor session has a nice selection of 6 papers. IEDM publishes figures from two of the presentations:

16.4 Near-infrared Sensitivity Enhancement of a Back-illuminated Complementary Metal Oxide Semiconductor Image Sensor with a Pyramid Surface for Diffraction Structure,
I. Oshiyama, S. Yokogawa, H. Ikeda, Y. Ebiko, T. Hirano, S. Saito, T. Oinoue, Y. Hagimoto, H. Iwamoto, Sony Semiconductor

Boosting Near-Infrared Sensitivity in CMOS Imagers: Backside-illuminated CMOS image sensors are ubiquitous in camera phones, and there is a growing demand for them to be able to handle near-infrared (NIR) light frequencies so that they can be used in iris scanning, facial recognition and motion-sensing applications. However, the NIR-sensitivity of silicon CMOS image sensors has been inadequate. The simplest way to enhance it would be to make the photo-absorption layer thicker, but that would require substantial capital investment in manufacturing equipment like high-energy ion implanters to be able to work with the thicker layer. Instead, Sony researchers developed a way to increase the NIR sensitivity of a 2-megapixel backside imager by building pyramidal light-diffraction structures on its surface. These 400nm structures diffract and trap the light coming to each pixel. The researchers also isolated each 1.12µm pixel from its neighbors by means of a special treatment process and used deep trench isolation to reduce crosstalk. They achieved a 50% increase in NIR sensitivity and a quantum efficiency of 30% at 850nm. Image resolution and levels of dark current (i.e., electrical “noise”) were not compromised.

The image is a photomicrograph of a section of a backside-illuminated CMOS image sensor with a cell size of 1.12µm and pyramid surfaces for diffraction (PSD) and deep-trench isolation (DTI) structures. The PSD pitch was 400 nm.

16.3 Back-side Illuminated GeSn Photodiode Array on Quartz Substrate Fabricated by Laser-induced Liquid-phase Crystallization for Monolithically-integrated NIR Imager Chip,
H. Oka, K. Inoue, T. T. Nguyen*, S. Kuroki*, T. Hosoi, T. Shimura and H. Watanabe, Osaka University, *Hiroshima University

Back-side illuminated single-crystalline GeSn photodiode array has been demonstrated on a quartz substrate for group-IV-based NIR imager chip. Owing to high crystalline quality of GeSn array formed by laser-induced liquid-phase crystallization technique, significantly enhanced NIR photoresponse with high responsivity of 1.3 A/W was achieved operated under back-side illumination.

Record Performance from GeSn Backside Imager: An Osaka University-led team will report on a backside-illuminated germanium-tin (GeSn) photodiode array with a high responsivity of 1.3 A/W at 1550nm, a record high on/off ratio of 5 decades, and low dark current of 10-3 A/cm2. They formed the large-area, tensile-strained and single-crystal GeSn device on a quartz substrate by using laser-induced liquid-phase crystallization. Because quartz has a high transparency to NIR frequencies, and can be combined directly with silicon, this work opens up the possibility to monolithically integrate high-performance GeSn NIR imagers with silicon CMOS circuitry.

In the schematic on the left, (a) is an illustration of lateral liquid-phase crystallization of GeSn wire on a quartz substrate by rapid thermal annealing, while (b) is an in-situ observation of lateral liquid-phase growth of GeSn wire.

At right is a schematic of the fabrication process and an optical image of a single-crystal GeSn n+/p photodiode array on a quartz substrate. P+ implantation was performed to form the n+ regions of the diodes.